A Ferroelectric Random Access Memory (FRAM (registered trademark)) has achieved nonvolatile storage characteristics of stored data (for example, holding performance for about ten years), and excellent characteristics of a high speed data write-in performance for about several 10 ns for example, by using hysteresis characteristic which a ferroelectric capacitor has.
On the other hand, since it is necessary to drive comparatively large capacitor for control of the hysteresis characteristic of the ferroelectric capacitor, it is difficult to achieve a high speed operation of a Static Random Access Memory (SRAM) level having access time for about several ns for example, in the present condition. Moreover, since the characteristics of the ferroelectric capacitor deteriorated gradually whenever it repeated a polarization inversion, there was a problem that the number of times of data rewriting is limited to about 1014 times per one capacitor.
In order to solve the problem, there is a method of using a ferroelectric capacitor as a mere capacitative element at the time of normal operation mode, performing a Dynamic Random Access Memory (DRAM) mode operation for holding data with quantity of electrically charged up charges, and performing an FRAM mode operation for non-volatilizing data using the hysteresis characteristic only at the time of power supply cutoff (for example, refer to Patent Literature 1 and Patent Literature 2).
In the method, since an improvement in a speed of the operation can be achieved by not using the hysteresis characteristic at the time of normal operation mode, but reducing a capacitor to drive, and polarization inversion is not occurred, it is effective in the ability to suppress a characteristic degradation of a device.
In the DRAM mode, it becomes advantageous to high speed operation so that a Bit Line (BL) capacitor to which a memory cell is connected is small, but on other side, in the FRAM mode, a large Bit Line (BL) capacitor is needed in order to read a residual polarization electric charge. Since the BL capacitor can be applied small by the trade-off only in the range in which the FRAM mode can operate, the improvement in the speed has limitations.
When holding data also in a power OFF period, it is necessary to perform data write-in with the FRAM mode for a memory cell which is operating in the DRAM mode, and to non-volatilize the data, at the time of power supply cutoff. Accordingly, the operating time in the FRAM mode needed at the time of power supply cutoff becomes long as memory space becomes large.    Patent Literature 1: Japanese Patent Application Laying-Open Publication No. H06-125056    Patent Literature 2: Japanese Patent Application Laying-Open Publication No. H08-203266